| 摘要 |
A high speed logic circuit with reduced quiescent current receives a plurality of input signals and performs a predetermined logic operation on the plurality of input signals. The predetermined logic operation may be, for example, a comparison of true and complement input signals, or a logical AND of two input signals. In response to the predetermined logic operation, first and second bipolar transistors coupled between first and second power supply voltage terminals are alternately made conductive to provide an output signal therebetween at ECL levels. A biasing portion ensures a proper voltage on a base of the second bipolar transistor. A current portion draws current from the base of the second bipolar transistor until the voltage of the output signal reaches a logic low voltage, and then makes the second transistor nonconductive, keeping the quiescent current of the circuit to a minimum.
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