发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To transmit an output digital signal synchronized correctly with an input digital signal having a transmission rate by setting the frequency of an output digital signal at a level accordant with the center frequency information when the frequency information on the output digital signal is set out of a range of the boundary frequency information set previously. CONSTITUTION:A 1st or 2nd center frequency information DFSC or DFLC and the boundary frequency information DFSU and DFSD or DFLU and DFLD are set based on the 1st or 2nd transmission rate of an input digital signal. Then the frequency of an output digital signal CKOUT is set at a level accordant with the information DFSC or DFLC when the frequency information DCNT of the signal CKOUT is set out of the range of the information DFDU and DFSD or DFLU and DFLD. Thus the signal CKOUT synchronizing correctly with the input digital signal having the 1st or 2nd transmission rate can be transmitted.
申请公布号 JPH03181224(A) 申请公布日期 1991.08.07
申请号 JP19890319146 申请日期 1989.12.09
申请人 SONY CORP 发明人 FUKUDA SHINICHI
分类号 G11B20/10;H03L7/06;H04L7/033 主分类号 G11B20/10
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