| 摘要 |
PURPOSE:To secure both the holding time and the set-up time without using an external clock delay means by storing previously the selection data in a memory and controlling a selector to take a desired phase out of the clock delay means. CONSTITUTION:Plural clocks of different phases are produced and the optimum one of these clocks is selected as the latch timing. Hereafter the clock of the optimum phase is supplied to a flip-flop circuit 16 via a memory 28 and a selector 13. Thus it is not required to calculate the delay time when a circuit is designed but just required to design the circuit within a some controllable range in terms of a latching clock. Consequently, both the holding time and the set-up time can be easily satisfied without using the external clock delay means. Furthermore the circuit design is facilitated together with the improvement of the yield. |
