发明名称 BIT SYNCHRONIZATION SYSTEM
摘要 <p>PURPOSE:To stably reproduce a data by fetching an external input data with an internal clock even when there is any phase difference between the external clock and the internal clock to synchronize the external data with the internal clock. CONSTITUTION:An input data DATAIN(D0) is latched by a flip-flop (ESFF1) at a leading edge of a clock whose frequency is twice that of an external clock CK1 and generated from the clock CK1 and then outputted. It is the function of the bit synchronization circuit that the D0 data is formed into an output data (DATAOUT) synchronously with the internal clock (CK2) and the circuit is normally operated even when any phase difference exists between the clocks CK1 and CK2. Thus, the data is reproduced stably.</p>
申请公布号 JPH03101431(A) 申请公布日期 1991.04.26
申请号 JP19890237071 申请日期 1989.09.14
申请人 HITACHI LTD;HITACHI COMMUN SYST INC 发明人 YAMAMOTO MASAMI;TAKAGI HIROSHI
分类号 H04L7/00 主分类号 H04L7/00
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