| 摘要 |
<p>PURPOSE:To decrease the required memory quantity more than that for a conventional delay device by separating a high-order bit and a low-order bit of a data and storing them into an FIFO. CONSTITUTION:An input data is separated into a high-order bit and a low-order bit by a bit separator 2, the low-order bit is delayed as it is by an FIFO 12 and inputted to a bit mixer 16. On the other hand, the high-order bit is decided whether or not it is to be stored by a significant information decider 5. The decision information 6 is used as a write enable signal by an FIFO 8, and further delayed by an FIFO 10 and used as a read enable signal of the FIFO 8. Only when the write is enabled at the FIFO 8 in the high-order bit 3 in the information 6, a data is inputted to the FIFO 8. Moreover, the data in the FIFO 8 is read only when the data is enabled to read by decision information 11.</p> |
