| 摘要 |
<p>PURPOSE:To improve the arithmetic efficiency of a processor by dividing respective frame memories into plural memory units, and allowing the all processors to access the respective divided memories. CONSTITUTION:The subject processor is provided with a control part 1, which controls the encoding/decoding of a picture, plural frame memories 3, which are individually expanded by the control part 1 whose connection can be altered and whose inside is divided into plural memories M1 to M4, and plural processors 2 which are individually connected to said control part 1 so as to access the respective memory units M1 to M4 in the frame memories 3 and whose connection is alterable. Further processing priority is applied to the frame memories M1 to M4 whose processing is delayed.</p> |
