| 摘要 |
PURPOSE:To attain a decoder circuit having two output signals with low power consumption by using at least the 1st MOSFET having its drain and source connected to the 1st power supply and the 1st terminal respectively and the 2nd MOSFET having its drain connected to the 1st terminal to latch the 2nd signal and to deliver the 3rd signal. CONSTITUTION:The signals delivered to a terminal (b) for a period phi1 are supplied to a gate, and a selected signal of a high level is delivered to the terminal (b) by an MOSFET MAn+5 having its drain used as a power supply VCC. Under such conditions, a high level of (VCC-VT) is delivered to a terminal (c) for the period phi1. Then an MAn+8 is energized and latched and a signal of a high level is delivered to a terminal (d) in the next period phi2 as a write word signal. In case non-selection at a low level is kept at the terminal (b) in the period phi1, a low level is kept by an MAn+6 which supplies a clock signal phip having an extended latter half a high level to a gate. This low level is latched by a transfer gate of an MAn+7. Then the MAn+8 is not conducted and to keep a low level which is discharged in said period phi1 at the terminal (d). |
