发明名称 METHOD FOR GENERATING TEST PATTERN FOR SCANNING CIRCUIT AND METHOD FOR DIAGNOSING TROUBLE OF FIXED FORM LOGICAL CIRCUIT
摘要 PURPOSE:To facilitate and shorten the process and time of diagnostic design by classifying troubles of the scanning circuit by operation sequences for detecting the trouble in advance and storing scanning operation sequences for detecting the trouble of each classified trouble group. CONSTITUTION:Assuming such a single degenerative trouble model that there is one trouble wherein the value of the input and output signal lines of a logic element in the circuit is fixed at 0 and 1, only one trouble is assumed in the scanning circuit. Therefore, when specific trouble is assumed, a scanning operation sequence for detecting the trouble can be determined. In other words, when the scanning operation sequence is determined, the trouble detected by it is determined. Namely, troubles detected by a certain scanning operation sequence are gathered and then grouped. Then a scanning operation sequence is selected properly according to a table to determine a set of scanning operation sequences for a test which detect all troubles. Test patterns are generated for all sets and the trouble detection rate is increased up to 100%.
申请公布号 JPH02210279(A) 申请公布日期 1990.08.21
申请号 JP19890260025 申请日期 1989.10.06
申请人 HITACHI LTD 发明人 HAYASHI NOBUYUKI;NIIYA TAKAO;TANDAI MIYAKO;EBARA TAKAFUMI;MORIWAKI IKU
分类号 G01R31/28;G01R31/3183;G06F11/22 主分类号 G01R31/28
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