发明名称 SERIAL DATA RECEIVING CIRCUIT
摘要 PURPOSE:To easily receive serial data even if a bit rate of the other party side is not known especially in a transmitting side and a receiving side by providing a clock generating part, a clock selecting part, a start bit detecting part, etc. CONSTITUTION:Plural clock groups obtained by bringing a reference clock to frequency division are always outputted from a clock generating part 1, and a clock selecting part 3 selects one clock in the clock group. On the other hand, a receiving bit inputted to a start bit detecting part 2 detects a prescribed start bit contained in receiving data, based on a clock outputted from the selecting part 3. While the detecting part 2 does not detect the start bit, the selecting part 3 selects successively from a higher clock or a lower clock in plural clocks, and when the start bit is detected, the output clock of the selecting part 3 is selected and fixed. In such a way, a data transfer part 4 transfers the receiving data by a clock of the time when the start bit is detected, therefore, even if each bit rate is not known in advance in the transmitting and receiving sides, the data can be transferred.
申请公布号 JPH02202738(A) 申请公布日期 1990.08.10
申请号 JP19890023164 申请日期 1989.02.01
申请人 FUJITSU LTD 发明人 SUZUKI SHOJI;NAKAYAMA SHUNICHI;SHIRAI HIROAKI;NARA KOICHI
分类号 H04L25/40;H04L7/02;H04L7/04 主分类号 H04L25/40
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