发明名称 TEST METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To eliminate defective decision, and to test the integrated circuit efficiently by a method wherein measured values obtained through measurement are compared with each of correlation curves, acceptable values or defective values are decided at every correlation curve, the results of acceptable or defective decision are logically multiplied at every correlation curve, and acceptable or defective values are finally decided. CONSTITUTION:A segment joining a point 1 and a point 5 is first acquired previously because a section surrounded by points 1, 5, 3, 6 indicates the range of acceptable articles. Likewise, segments each joining the point 5 and the point 3, the point 3 and the point 6 and the point 6 and the point 1 are obtained. Positions at any sides to each segment of points severally using DC current amplification factors separately measured and resistance values as Y coordinates and X coordinates are decided. When the measuring points are positioned at the lower sides to the segment joining the point 1 and the point 5, articles are decided as acceptables. Lastly, these four decision is logically multiplied, and employed as the final decision.
申请公布号 JPS5851529(A) 申请公布日期 1983.03.26
申请号 JP19810150397 申请日期 1981.09.22
申请人 NIPPON DENKI KK 发明人 ONOZAWA TOSHIAKI
分类号 G01R31/26;H01L21/66;(IPC1-7):01L21/66 主分类号 G01R31/26
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