| 摘要 |
<p>A central processing unit for a data processor having an emulation function comprises a register file coupled to supply data to a main data bus and to receive data through the main data bus, and also coupled to output data to a sub data bus, an arithmetic and logic unit having a first input coupled to the main data bus so as to receive data through the main data bus from the register file and a second input coupled to the sub data bus so as to receive data through the sub data bus from the register file, the arithmetic and logic unit having an output coupled to the main data bus so as to output the result of operation to the register file, and a general program status register and an emulation status register respectively coupled to the arithmetic and logic unit so as to receive program status information generated as the result of operation of the arithmetic and logic unit. The general program status register and the emulation status register are also coupled to the main data bus so as to output the program status information and to be loaded with program status information. The general program status register and the emulation status register are controlled in such a manner that when the central processing unit is in an emulating condition, the emulation status register are is brought into an active condition, and when the central processing unit is in a condition other than the emulating condition, the general program status register is brought into an active condition.</p> |
