| 摘要 |
PURPOSE:To reduce the load on a CPU and improve its versatility by fetching data and performing serial-parallel conversion, and reading the data by a CPU in parallel with an interruption signal. CONSTITUTION:When serial interfaces corresponding to signal connectors 11 and 12 are connected, the bit signals of data from the connected interfaces are fetched to a shift register 15 for serial-parallel conversion with a clock signal generated by a timing circuit 17. Then when a specific number of bit signals are fetched, the timing circuit 17 sends an interruption signal to the CPU, which reads data out of the shift register in parallel. The fetch of bit signals to the shift register 15 is timed with the bit signal from the interface whose output timing of the bit signal is slowest among various interfaces. Consequently, data can be read by connecting various interfaces and the load on the CPU is reducible. |
