| 摘要 |
PURPOSE:To surely eliminate only a false pulse without being adfected by secular change by using a digital circuit consisting of a counter means and a decision means. CONSTITUTION:The counter means 1 performs a count operation to count a clock signal during a first logic level period when an input signal is set at a first logic level. The decision means 2 resets a count value by supplying a reset signal to the counter means 1 when the count value counted by the counter means 1 goes less than a prescribed count value. Simultaneously, an input pulse signal is outputted as an output pulse signal after a signal part corresponding to the first logic level period of the input pulse signal is converted to a second logic level before being transited to the first logic level. Also, when the count value of the counter means 1 goes higher than the prescribed count value, the input pulse signal is outputted as the output pulse signal as leaving its logic level as it is. In such a way, it is possible to surely absorb and eliminate only the false pulse. |
