发明名称 OUTPUT CIRCUIT
摘要 PURPOSE:To reduce the fluctuation of a power supply at output load charge/ discharge and a ground potential and to decrease the through-current of the output circuit itself by adopting the constitution such that 3 each of P-channel and N-channel MOS transistors(TRs) and one inverter are connected in the specific relation. CONSTITUTION:Just after the potential at an input terminal 1 changes from a low level to a high level (0V to VDD potential), the P-channel MOS TR 3 is turned from ON to OFF and the N-channel MOS TR 5 is turned from OFF to ON. Then the gate voltage of the P-channel MOS TR 6 is slowly decreased by the output resistor of an inverter 9 and the ON-resistance of the N-channel MOS TR 2. Thus, the N-channel MOS TR 7 is turned off at first, then the P-channel MOS TR 6 is slowly turned on. Thus, no through-current flows from the power supply to ground. Moreover, since the gate voltage of the TR 6 is slowly decreased, the movement of the potential at an output terminal 8 is slow. Thus, the fluctuation of the power ground potential for the power ground impedance is less.
申请公布号 JPH0229028(A) 申请公布日期 1990.01.31
申请号 JP19880179401 申请日期 1988.07.18
申请人 NEC CORP 发明人 KIKUCHI KOICHI
分类号 H03K19/0175;H03K17/687;H03K19/00 主分类号 H03K19/0175
代理机构 代理人
主权项
地址