| 摘要 |
A data processing system consists of a number of processing modules and memory modules interconnected by a common bus. If a memory module is not free to accept addresses or data from the bus, it asserts an address wait (AW) signal or a data wait (DW) signal, as the case may be. When a processing module sends an address or data over the bus, it normally holds it there for one clock cycle only. However, if the relevant wait signal AW or DW is asserted, the address or data is held on the bus until this wait signal is removed. This arrangement avoids the need for acknowledgement on the bus, and hence speeds up the transaction of information. |
