摘要 |
Circuit for increasing the voltage rating of a CMOS circuit which contains at least a first and at least a second partial circuit (3, 5), the operating potentials of which are different and which are coupled to one another via a first and a second circuit node (k1, k2). In order to limit the voltage, use is made of a cascade circuit between the first and second circuit nodes (k1, k2), having at least one p-channel transistor (t) the gate connection (G) of which is supplied with a fixed potential (HV) and the well connection (W) of which is approximately at the corresponding source potential (Figure 3). <IMAGE> |
申请人 |
DEUTSCHE ITT INDUSTRIES GMBH, 79108 FREIBURG, DE |
发明人 |
BLOSFELD, LOTHAR, DIPL.-PHYS., 79874 BREITNAU, DE;THEUS, ULRICH, DR.-ING., 79194 GUNDELFINGEN, DE;MOTZ, MARIO, DIPL.-ING., 79346 ENDINGEN, DE |