| 摘要 |
PURPOSE:To balance bit-line additional capacitance and dummy bit-line load capacitance, and to decide cell reading data positively even when voltage fluctuation is generated by arranging the connection mode of a memory cell transistor to a bit line and the connection mode of a cell transistor for dummy capacitance to a dummy bit line. CONSTITUTION:Each drain diffusion region 11 of memory cell transistors MC for storing data is connected to a bit line not shown through drain contact sections 13. The source regions 12 of the transistors MC arranged in the row direction are connected respectively to a power line not shown through a source contact region 14 at that time while a transistor DMC for a dummy cell is constituted in the same manner as the MCs in a column separate from the MCs, and is connected to a dummy bit line not shown by the drain contact section 13 of the transistor DMC. Cells and dummies are connected mutually in a source region 12, and a plurality of dummy capacitance cells DC disposed in the same column direction as the transistor DMC are separated from the adjacent region 12 and kept floating. |
