| 摘要 |
In a data processing unit which includes first and second buses, and an arithmetic and logic unit (21), there are provided a register file (22) connected between the first and second buses, for storing data on the second bus, the register file including a plurality of register portions (22a, 22b, 22c) having a capacity equal to or exceeding a minimum data length of data processed in the ALU (21), and a bypass circuit (23) connected between the first and second buses for bypassing data on the second bus to output the data to the first bus per a unit of the minimum data length, the bypass circuit including a plurality of bypass lines (23a, 23b, 23c) each having the minimum data length. A control circuit (24, 25) controls data read and data write for the register file per a unit of the minimum data length and controlling the bypass circuit so as to bypass the data on the second bus to the first bus per a unit of the minimum data length.
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