| 摘要 |
In order to assess the accuracy of the positioning of a flip-chip solder bond between a substrate 4 and an integrated circuit and/or micro-optic device 2, rows of alignment marks 12, 14, 20, 22, 24 are formed together with the arrays of metallised solderable pads on the cooperating surfaces of the substrate and chip so that when the bond is formed, the row of alignment marks cooperate to form a vernier scale to determine the accuracy of the bond. The marks may be formed as metallised regions having solder bumps formed thereon for visibility by means of X-rays. <IMAGE> |
