发明名称 |
Clock signal generator |
摘要 |
The clock signal generator for generating non-overlapping polyphase clock pulses having no overlapping period of time where the clock pulses have a high level at the same time, comprises a clock signal generation control means provided for each of the polyphase clock pulses so that a clock signal on a signal path where the largest delay is caused among at the signal paths of one phase is used to prevent clock signal generation in the other phases.
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申请公布号 |
US4866310(A) |
申请公布日期 |
1989.09.12 |
申请号 |
US19870113309 |
申请日期 |
1987.10.28 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ANDO, HIDEKI;NAKABAYASHI, TAKEO |
分类号 |
G06F1/06;H03K5/15;H03K5/151 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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