发明名称 EPROM
摘要 <p>PURPOSE:To improve the efficiency of writing by providing a substrate voltage generating circuit made to the state of operation selectively in writing operation in an EPROM and applying a negative substrate voltage to a semiconductor substrate at the time of the writing operation of the EPROM. CONSTITUTION:A substrate back bias voltage generating circuit VbbG made to the state of operation selectively at the time of a writing operation mode is provided, and negative substrate back bias voltage -Vbb is supplied to the semiconductor substrate of an EPROM. In such a case, the value of substrate back bias voltage -Vbb is made to about -2V which is close to the central value of substrate potential Vsub at which write efficiency Ew becomes flat. Thence, hot hole induced in the channel part of an FAMOS transistor is absorbed through a semiconductor substrate P-SUB, and even when the substrate potential Vsub is raised by the voltage drop of substrate resistance Rs, the substrate potential Vsub does not exceed OV. Accordingly, since high voltage Vpp for writing applied to the drain and control gate of the FAMOS transistor is not lowered substantially, the lowering of efficiency of writing Ew can be prevented.</p>
申请公布号 JPS6352399(A) 申请公布日期 1988.03.05
申请号 JP19860195315 申请日期 1986.08.22
申请人 HITACHI LTD 发明人 NAKAMURA YASUHIRO;WADA TAKESHI
分类号 G11C17/00;G11C16/04;G11C16/06 主分类号 G11C17/00
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