| 摘要 |
<p>A data decoding circuit receives an input signal comprising a sequence of pulses and generates a digital data output signal and timing signals in response thereto. The circuit includes a phase-locked loop which generates timing signals in response to the input signal and an offset signal from a data separator circuit. The data separator circuit generates the digital data output signal and the offset signal, which measures the degree of correlation between the input signal as received by the data separator and the timing signal from the phase-locked loop, thereby obviating the need to match the data separator circuit closely to the phase-locked loop.</p> |
