| 摘要 |
An integrated circuit chip has circuitry for converting a binary coded value to an analog value. The chip includes first and second matrices each defined by rows and columns. The rows and columns have sources at different positions for producing currents in response to binary signals coding for the binary value. Each row in the first matrix is connected to a row in the second matrix on a reverse-image basis. For example, if each matrix has thirty two (32) rows, rows 1 and 32 in the first matrix are respectively connected to rows 32 and 1 in the second matrix. The rows in the matrices are sequentially selected in a pattern providing particular convergences and divergences of successive paris of such rows in each matrix. Such sequential selection provides progressive convergences and then progressive divergences of the rows in each of the successive pairs in each matrix about the center line as a reference. Such progressive convergences and divergences may occur in at least a pair of successive cycles. When such a selection occurs, the selected rows in each matrix in one cycle are interleaved in such matrix with the selected rows in the other cycle. In this way, compensation may be provided on the chip for second order errors such as result from stresses in the chip. |
