发明名称 PSEUDO FAULT CIRCUIT
摘要 PURPOSE:To check the normal properties of various error detecting circuits at one time by using plural error forcibly generating circuits which produce errors to various signal groups and plural error detecting circuits which detect the occurrence of errors. CONSTITUTION:When the error forcibly generating signal 500 is supplied to various error forcibly generating circuits 1-4, the error factors are given to various signal groups 100-400 for output of a command signal group 101, an address signal group 201, a read data signal group 301, and a write data signal group 401. Receiving these signal groups, various error detecting circuits 9-12 deliver various error detecting signals 104, 204, 304 and 404 at one time. Thus the output of an AND circuit is equal to 1 as long as the circuits 9-12 are all normal and then equal to 0 if only one of these circuits 9-12 has abnormality.
申请公布号 JPS6464039(A) 申请公布日期 1989.03.09
申请号 JP19870221395 申请日期 1987.09.04
申请人 NEC CORP 发明人 YAMAUCHI MAKOTO
分类号 G06F11/22 主分类号 G06F11/22
代理机构 代理人
主权项
地址