发明名称 SYNCHRONOUS BUS CONTROLLER
摘要 PURPOSE:To enable a fast processing by a bus user synchronizing with a basic clock to be realized, by operating a bus arbitration circuit synchronizing with one basic clock out of plural bus users. CONSTITUTION:Users A10 and B20 send bus usage right requests 101 and 201 to a bus arbitration part 40 at the time of using a bus. The arbitration part 40, after taking the synchronization of the request 101 at a synchronization circuit C44 by using a clock 602, performs arbitration at an arbitration circuit 41, and sends but usage rights 401 and 402, by synchronizing the usage right 401 with a clock 601 at a synchronization circuit A42 and sending the usage right 402 as it is. In such a case, data transfer between the user A10 and a resource C30 is performed synchronizing with the clock 601 via a bus 501. In case of the user B20, the data transfer between the resource C30 is performed similarly synchronously with a clock 602.
申请公布号 JPS63316153(A) 申请公布日期 1988.12.23
申请号 JP19870152329 申请日期 1987.06.18
申请人 NEC CORP 发明人 KANAZAWA TORU
分类号 G06F13/368;G06F13/364 主分类号 G06F13/368
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