发明名称 DATA PROCESSOR
摘要 PURPOSE:To perform the state recovery at high speed by designating one of two register files containing the same number of registers set in 1:1 correspondence as a master file according to the value of a selectable flag. CONSTITUTION:An instruction executing unit 215 contains a master register file 305 and a saving register file 310 which contain the same number of registers set in 1:1 correspondence. While a master buffer selection signal generator 315 contains a selectable flag to give an instruction for selection of the one of both files 305 and 310 that is first read out for each of those registers set opposite to each other. Then an executing environment set at a certain prolog time point is saved into the file 310 and said flag is set again to secure a state where the file 310 is read out as long as the processing is carried out with use of the file 305. Thus the executing environment is recovered at high speed.
申请公布号 JPS63247836(A) 申请公布日期 1988.10.14
申请号 JP19870079657 申请日期 1987.04.02
申请人 HITACHI LTD 发明人 HIRAYAMA YOICHI;KUROSAWA KENICHI;BANDO TADAAKI;NAKANISHI HIROAKI
分类号 G06F9/44 主分类号 G06F9/44
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