发明名称 DROP OUT DETECTING CIRCUIT
摘要 PURPOSE:To enable even drop out in a short period to be detected, by forming a circuit with four pairs of differential pair transistors, and controlling the timing of a detected output by the time constant of a capacitor. CONSTITUTION:When the differential pair transistors (TR) TRQ1 and Q3 are turned on and TRs Q2 and Q4 are turned off in two pairs of differential pair transistors on input sides by inputs from terminals 11a and 11b. the capacitor C1 connected to the common emitter of the two pairs of differential pair transistors on output sides is discharged via the two pairs of differential pair transistors TRQ8 connected to TRs Q6 and Q7 being connected to a bias power source Vb, and the TRQ1. The capacitor C1 is also discharged at the time of inverting the input similarly, and the TRs Q6 and Q7 are turned OFF, and no current flows, and the detected output goes to an H, and when the drop out is generated, the discharge of the capacitor C1 continues, and the detected output goes to an L with the timing corresponding to the discharge time constant of the capacitor C1. Therefore, it is possible to detect even the drop out in the short period such as one wavelength of an FW signal, etc., by selecting the dsicharge time constant of the capacitor C1.
申请公布号 JPS63241765(A) 申请公布日期 1988.10.07
申请号 JP19870076642 申请日期 1987.03.30
申请人 TOSHIBA CORP 发明人 AMAMOTO TORU;OGAWA ATSUSHI
分类号 H04N5/94;G11B20/06 主分类号 H04N5/94
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