| 摘要 |
PURPOSE:To double the working cycle of an internal circuit and to realize the fast working speed of a memory device by providing two address generating circuit groups to a serial address signal processing circuit so that the output signals of the address generating circuits are produced double. CONSTITUTION:The drive signals of output lines R1 and R2 are activated by a signal produced by dividing an external clock signal and an adverse phase signal in response to the value of an address bit A1. In other words, the line R1 is activated with an odd start address so that a serial address generating circuit C1 is driven and an output line S1 can be selected. While the line R2 is activated with an even start address so that a serial address generating circuit C1+1 is driven and can be selected. Thus the circuits C1 and C1+1 of two systems can be activated by an activating signal P1. As a result, the working cycle of an internal circuit is doubled to realize the fast working speed with a memory device.
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