发明名称 INTER-PROCESSOR COMMUNICATION SYSTEM
摘要 PURPOSE:To shorten the waiting time of a processor by performing the communication via a common bus route for the information having no direct relation with exchange processing and via a highway for the information having a direct relation with the exchange processing respectively. CONSTITUTION:Various types of data having direct relation with the exchange processing the processor of distribution stage and the processor 3 of line concentration stage which are needed for formation of a channel are transmitted and received through the route of the processor 3, a data transmitting/receiving device 4, a line concentration switch 2, a highway 8, a distribution switch 5, a data transmitting/receiving device 7 and a distribution stage processor 6. A common bus 9 is used for the data having no direct relation with the exchange processing such as an initial program loading data on the processor 3, the start instruction and the test result of the test function for the processor 3, a traffic data and its instruction, a charging data and its request instruction, etc.
申请公布号 JPS59119994(A) 申请公布日期 1984.07.11
申请号 JP19820226808 申请日期 1982.12.27
申请人 HITACHI SEISAKUSHO KK 发明人 KOBAYASHI HIDEO;MIYAZAKI KATSUYUKI
分类号 G06F15/16;G06F15/177;H04Q3/545 主分类号 G06F15/16
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