发明名称 LOOP BACK CIRCUIT
摘要 PURPOSE:To improve the profitability of a loop back circuit by cascading one- bit registers by the share of one frame length through separating means and thus constituting a shift register, controlling a specified separating means and dividing the shift register into two front and rear part, and interposing the partial shift registers in loop back paths for digital signals in respective directions. CONSTITUTION:A specific separating means 800 is controlled to divide the shift register consisting of registers 700 into two shift register parts. One partial shift register is interposed in a loop back path for a digital signal in one direction and the other partial shift register is put in a loop back path for a digital signal in the other direction. Consequently, this couple of shift registers delay the signals in both directions properly and the profitability of the loop back circuit is improved.
申请公布号 JPS63191432(A) 申请公布日期 1988.08.08
申请号 JP19870023901 申请日期 1987.02.04
申请人 FUJITSU LTD 发明人 ISHII YOSHINORI
分类号 H04L1/14;H04L13/00;H04L29/14 主分类号 H04L1/14
代理机构 代理人
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