| 摘要 |
PURPOSE:To reduce the number of times of carry detection and to shorten arithmetic processing time by providing the titled multiplier with a rounding/ carry detecting circuit for detecting carry based on a carry signal obtained from a mantissa part and rounding. CONSTITUTION:A carry signal from a mantissa part arithmetic circuit 20, a mantissa part bit to be a multiplied result and a code bit from an exponential part arithmetic circuit 10 are supplied to the rounding/carry detecting part 30 to judge carry and rounding. The detecting circuit 30 corresponding to respective states, i.e. (1) when both carry and rounding are not included, (2) when only carry is generated, (3) when both rounding and carry are generated, and (4) when only rounding is executed, and controls selectors 291, 271 in the circuit 20 and the circuit 10. Consequently, the number of times of carry detection is only once, so that the arithmetic processing time can be shortened.
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