发明名称 CLOCK EXTRACTING CIRCUIT
摘要 PURPOSE:To make it difficult to be affected by noise and reduce the circuit shape by detecting the rise point and the fall point of a binary FSK demodulated signal restored to a square wave to generate pulses and operating OR between them. CONSTITUTION:The binary FSN demodulated signal is restored to a square signal by a comparator 1, and the output of a rise point detecting circuit 2 is as shown in a figure (b) if this circuit 2 is so constituted that a pulse is generated at the rise point of the square signal. The constant of a used element is properly selected to set the width of the pulse to a half period of the demodulated signal. The output of a fall poin detecting circuit 3, which is so constituted that a pulse is generated at the fall point of the square signal, is as shown in a figure (c). When pulses shown in figures (b) and (c) are inputted to an OR circuit 4, a pulse whose width is a half period is generated at each time of inversion of the demodulated signal as shown in a figure (d). Consequently, since a double frequency component is generated if an input signal is random, the signal is allowed to pass a band-pass filter 5, thereby extracting a clock component.
申请公布号 JPS63187744(A) 申请公布日期 1988.08.03
申请号 JP19870018188 申请日期 1987.01.30
申请人 NEC CORP 发明人 ITO TOSHIKI
分类号 H03K5/00;H04L7/00;H04L7/027;H04L27/156 主分类号 H03K5/00
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