发明名称 |
DYNAMIC MEMORY REFRESH AND PARITY CHECKING CIRCUIT |
摘要 |
<p>A circuit for use in conjunction with a microprocessor for refreshing, checking and correcting data signals stored in a dynamic memory. The circuit utilizes a direct memory access controller for transferring data signals stored in successive locations of the dynamic memory to a non-existent peripheral. Data signals appearing on a data bus as a result of the data transfer, are applied to a parity checking circuit for generating an interrupt signal to the microprocessor in response to detection of parity errors in the data signal. The microprocessor then performs a data recovery routine in which correct versions of the data signal stored in a non-volatile memory, are transferred for storage in the dynamic memory under control of a microprocessor. Parity errors in data signals stored in the dynamic memory are thus corrected prior to being accessed by the microprocessor.</p> |
申请公布号 |
CA1240066(A) |
申请公布日期 |
1988.08.02 |
申请号 |
CA19850488829 |
申请日期 |
1985.08.15 |
申请人 |
MITEL CORPORATION |
发明人 |
RAMSAY, JOHN R.;STYRNA, ZBIGNIEW B. |
分类号 |
G11C11/401;G06F11/10;G06F11/14;G06F13/28;G11C7/10;G11C11/4096;G11C29/00;G11C29/42;(IPC1-7):G06F11/10 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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