发明名称 MAXIMUM VALUE DETECTING CIRCUIT
摘要 PURPOSE:To execute an operation at a high speed by deriving OR of digits of the same level of each input, inhibiting the subsequent comparison even when OR is '1', a value of the digit concerned of its input is '0', and discriminating an input to which the inhibition is not executed until the last digit to be the maximum value. CONSTITUTION:The titled circuit is provided with an arithmetic means 1 provided on every digit, for developing plural inputs to be compared to binary numbers, respectively, and deriving OR of values of the respective digits of the same level by using an waveguide of an optical/electromagnetic wave or a space propagation, a control means 2 for generating a fact that the subsequent comparison is inhibited, to the succeeding all digits, when OR of each input is '1' with regard to an arbitrary, but a value of the digit concerned of its input is '0', and a discriminating means 3 for deriving OR with regard to each digit successively from the digit of the highest level, inhibiting the subsequent comparison as for an input in which its value is '1', but the digit concerned is '0', and discriminating the input to which the comparison is not inhibited until reaching the digit of the lowest level, to be the maximum value and outputting it. In such a way, from plural values, the maximum value can be detected at a high speed.
申请公布号 JPS63175922(A) 申请公布日期 1988.07.20
申请号 JP19870007436 申请日期 1987.01.17
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 HIRAKAWA YUTAKA
分类号 G06F7/02 主分类号 G06F7/02
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