| 摘要 |
<p>PURPOSE:To cope with an ultra-high-speed machine cycle and to upgrade the integration of a logic integrated circuit (IC) by providing such a logic IC as having FFs respectively at its own input and output parts. CONSTITUTION:There is only one-stage difference in the number of logical gate stages between a logical path from the FF 8b of a logic IC 8 through a connection wire 12 to the FF 10b of a logic IC 10 and that starting from the FF 9b of the logic IC 9 through a connection wire 13 reaching the FF 10b, therefore, signal delay time difference due to the passing through respective logical paths is small, hence an input signal pulse to the FF 10b will never have its width which is much shorter than one-phase clock. Also, between third logical path and fourth logical path that respectively run from the FFs 9b, 9c of the IC 9 through a connection wire 14 and reaching the FF 11a of a logic IC 11, there is no difference in the number of logical stage, hence there is also no difference in signal delay time through respective logical paths, and as a result, an input signal pulse to the FF 10b does not comes much shorter than a clock period.</p> |
