| 摘要 |
PURPOSE:To reduce the generation of passing-each-other noises generated when a read out clock signal overlaps with an internal clock signal, by preventing integral multiple relation between the frequency of the internal clock signal and that of the readout clock signal. CONSTITUTION:An input PCM signal 1 while synchronizing with a read clock signal 2 is inputted to a decoder for digital-analog conversion. Its output is supplied to a switched capacitor filter 4 to remove higher harmonic components, obtaining an output analog signal 5. The decoder 3 and switched capacitor filter 4 are controlled by timing control signals 7 and 8 from a control circuit 6. At this time, the frequency division ratio of the frequency divider in a PLL circuit 20 is selected properly so as to constitute the frequency of an internal clock signal 8 is not a multiple of the frequency of a readout clock signal 2. |
