| 摘要 |
PURPOSE:To attain pipeline processing at a high speed by providing a pair of address generating circuits to use one of them as a reading circuit and the other used as a writing circuit with addition of a delay and using both circuits for read, arithmetic and write of an image memory. CONSTITUTION:A pair of x/y address generating circuits are used. An x/y address generating circuit 2 produces a read address to read out a 2-dimensional image element 1. The data read out of the memory 1 is turned into 1/2 luminance by a 1-bit shift circuit 6 and then undergoes arithmetic with the input data given from the outside through an arithmetic circuit 3. While an x/y address generating circuit 5 produces a write signal to write data in the memory 1. Thus the old image data are synthesized with 1/2 luminance and hereafter the 1-frame preceding image data synthesized with 1/2 luminance together with the 2-frame preceding image data synthesized with (1/2)<2> luminance and so on. Thus the old images are always faded. Then the pipeline processing is attained by carrying out successively said operations synchronously with clocks.
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