| 摘要 |
PURPOSE:To eliminate a noise pulse included in an input signal by connecting 3-stage of D FFs controlled by a common clock and whose each Q output is inputted to its next stage in cascade and introducing a signal in compliance with the majority decision. CONSTITUTION:The 1st-3rd D FFs 1-3 are controlled by one and same clock CP. An input signal I is inputted to the 1st FF1, a signal QA from its output terminal Q is given to the 2nd FF2 and its output signal QB is inputted to the 3rd FF3. The outputs QA-QC of the FFs 1-3 are given to a majority decision circuit comprising NAND circuits 41-43 and an inverted OR circuit 5, from which a signal QD in compliance with the majority decision is outputted. Thus, a narrow pulse included in the input signal I is eliminated. Moreover, in activating the 2nd digital filter block 32 by using a signal CP2 being the frequency division 33 of the clock CP1, a wider noise pulse is also eliminated.
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