| 摘要 |
PURPOSE:To perform the assured test of a peripheral circuit of a memory cell by detecting the voltage applied to a chip enable terminal after dividing said voltage in three steps and therefore distributing at least two bit string for test cells to a small capacity element containing only one chip enable terminal. CONSTITUTION:When the voltage of a chip enable terminal -CE is set at 0- 1.5V, the output D1b, D2b and D4b are set at H levels. Then the information on a bit string RB for real cell is delivered to an output terminal O through an output terminal 4. While bit string TB2 and TB1 for the test cell are not selected since the outputs D5b and D3b are set at L levels. When the voltage of the terminal -CE is set at 6-12V, the D3b is set at an H level. Thus the train TB1 is selected. While the string TB2 is selected when the -CE is set at >=12V since the D5b is set at the H level. Thus the two trains TB1 and TB2 can be connected to a single unit of the circuit 4. |
