| 摘要 |
PURPOSE:To attain a frame synchronization with simple parallel trans mission lines by providing a frame synchronization circuit to one of the parallel transmission lines, detecting the phase difference between a frame synchronization information on this transmission line and a parallel synchronization information on another transmission line, and controlling a variable delay element corresponding to thus obtained phase difference. CONSTITUTION:A data 123 on the transmission line 100 is delayed by one bit with a one bit delay element 106, and outputted to a transmission line 103. The frame synchronization circuit 107 provides the frame synchronization by using a frame synchronization information F multiplexed with the delayed data 126 and latch pulses are transmitted to D latchs 108, 109, 110 at the position of the frame synchronization information F, and the frame synchronization information F is latched to the D latch 108, and data on the transmission lines 104, 105 are latched respectively to the D latches 109, 110. An exclusive logic circuit 111 compares the frame synchronization information F latched to the D latch 108 with the data on the transmission line 104 latched to the D latch 109, and outputs a control information to the variable delay element 113 in case of detecting a noncoincidence. |
