| 摘要 |
PURPOSE:To speed up the reading operation of a memory cell by checking charging to an inversion bit line or an inversion bit line making a pair when the bit line or the inversion bit line is fixed at a high level. CONSTITUTION:When the high level is written to the node 12 of a memory cell 1 of an unselected state, and a low level is written to a node 13 and the bit line 6 is low level, a load transistor 14 is turned on through an inverter circuit 18 and a load transistor 15 is turned off. At the time of reading, the inversion of a bit line 6 is made by charging by the power source 17 of an inverter circuit 10, and the inversion of an inversion bit line 7 is made by the difference of the discharge by an inverter circuit 11 and the charge by a power source 16. In this time, when the potential of the bit line 6 arrives at the threshold voltage of the circuit 18, the transistor 14 is turned off and prohibits the charging to the bit line 7, and accelerates the trailing of the bit line 7. Thus, the speed of reading operation of the cell 1 can be increased. |
