| 摘要 |
PURPOSE:To secure a wide lock range and capture range, by providing a control circuit which detects synchronism on the input of a phase comparator circuit by means of the output of a frequency dividing circuit and controls the gain of a DC amplifying circuit in accordance with the output of the detection. CONSTITUTION:When an input is stereo signals, phases of a 19-KHz stereo pilot signal and the output of a frequency dividing circuit 8 are compared with each other by means of a phase comparator circuit 9 and PLL control is started. Since a PLL circuit is not locked at the moment when the PLL control is started, no output is produced from a synchronism detecting circuit 11 and a stereo displaying lamp 13 is maintained at a no-light state and, as a result, a control circuit 14 does not operate. Accordingly, the gain of a DC amplifying circuit 10 becomes the relatively high 1st prescribed value and the capture range of the PLL circuit is widely maintained. When the PLL circuit is locked to the stereo pilot signal, the output of the circuit 11 is produced and the lamp 13 lights. Simultaneously, the circuit 14 operates and the gain of the circuit 10 becomes the 2nd prescribed value and, as a result, the phase jitter disappears. |
