| 摘要 |
PURPOSE:To reduce the tracking time by adding a circuit extracting the phase range of a reception signal and sending a reset signal to the phase synchronizing circuit if the phase of the reception signal is at the outside of a prescribed hase range to synchronize the phase of the clock with the phase of the reception signal. CONSTITUTION:A leading edge a recovered clock B is detected by a leading edge detection circuit 44 and an output signal C at each leading edge is fed to monostable multivibrator 42, 43. Its output signal is inputted to an ExOR gate 41, from which an ExOR output F is outputted and supplied to an AND gate 31. On the other hand, the leading edge of reception signal S(2), S(1) is detected by a phase detection circuit 2 and a detected output G is fed to an AND gate 31, where the AND condition is taken, resulting that a reset signal H is fed to a frequency divider circuit 13. The reset signal H is supplied also to monomultivibrators 42, 43 as well as the circuit 13. Then they are reset respectively at the trailing edge of the reset signal H. |
