| 摘要 |
PURPOSE:To enable a time constant set in analog fashion by means of a resistor and a capacitor to be set digitally, and to eliminate the variance of the time constant, by constituting a normal operation monitoring circuit for a CPU of a logic circuit. CONSTITUTION:The division signal 40 of a flip-flop 3 is inputted to the input D of a normal operation signal storage circuit 210, and simultaneously, it is inputted to the input, the inverse of R. Meanwhile, a normal operation monitoring signal 70 is inputted to the input C of the storage circuit 210. The normal operation monitoring signal 70 generates one pulse at least that is a normal operation signal (intervals where pulses are generated are shown as (a) and (b)) in a signal waveform in a peripheral interval T shown as oblique line when the CPU is operated normally, and when the CPU is operated abnormally (runaway), no pulse is generated in the interval T (the interval is shown as (c)). Also, the interval T corresponds to the 'Hi' state of the division signal 40 of a frequency-dividing circuit 200.
|
