| 摘要 |
<p>PURPOSE:To set the duration of a reset signal to an optional time by providing a counter to supply the reset signal continuously for an optional desired time. CONSTITUTION:When a power source is turned on, a flip flop 6 is cleared, and the value from a time setting part 5 is loaded to a counter 4, and counting is performed synchronously with a clock CLK. During this time, the Q output of the flip flop 6 is logical '0', and a processor 1 is reset. When contents of the counter 4 become zero, the flip flop 6 is set, and the Q output is returned to logical '1'.</p> |
