发明名称 ELECTRONIC COMPUTER CONTROL SYSTEM
摘要 PURPOSE:To reduce the activity ratio of a bus by selecting a required inseparable read/write signal out of signals outputted from a processor, and making perform a bus access. CONSTITUTION:When a reference to a storage device in which an inseparable readout/write signal 5 is at a level of 1 is generated, an address 7 and a data 8 at that time are stored at registers 28 and 29 respectively, and an FF22 is set at the level of 1. And at every reference to the storage device by a processor 1, an address is compared with the previous one stored at the register 28, and when they coincide with each other, a bus request signal 32 is set at a level of 0, thereby preventing a bus operation from being generated, and also, the data 8 at the register 29 is returned to the processor 1 as a result read out from the storage device. Meanwhile, by detecting a coincidence between the address signal 7 on a bus 2 and the address in the register 28 at a comparator 33, and detecting both that it is a write operation, and that it is not an inseparable signal by an AND gate 34, the FF22 is reset through an OR gate 21.
申请公布号 JPS62184564(A) 申请公布日期 1987.08.12
申请号 JP19860027493 申请日期 1986.02.10
申请人 NEC CORP 发明人 MITSUSAKA TOSHIO
分类号 G06F15/16;G06F9/52;G06F12/00;G06F13/18;G06F15/173;G06F15/177 主分类号 G06F15/16
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