发明名称 PROGRAM DEBUGGING DEVICE
摘要 PURPOSE:To efficiently execute a program debugging by using a debug memory giving a program running number of times. CONSTITUTION:A control circuit 8 brings a system to a debug mode. The address of the debug memory 7 is set to a counter 2. At every time an address is revised, the data read from the debug memory 7 is incremented by 1 by an increment circuit 9 and a data is written again in the buffer debug memory 7. After the end of debugging, when the control circuit 8 sets the system to the read mode, a read/write address switching circuit 6 selects a read address counter 5. In setting the address of the debug memory 7, the content of the memory 7 is read. The output from the debug memory 7 indicates how many times the program runs the address.
申请公布号 JPS62150443(A) 申请公布日期 1987.07.04
申请号 JP19850291425 申请日期 1985.12.24
申请人 NEC CORP 发明人 TSUCHIYA MASAKI
分类号 G06F11/28;G06F11/36 主分类号 G06F11/28
代理机构 代理人
主权项
地址