发明名称 BIT MULTIPLEX TYPE PACKET COMMUNICATION SYSTEM
摘要 PURPOSE:To eliminate the need for a high speed circuit to be applied to a high speed transmission line by operating a reception circuit, a transmission circuit and a terminal section at a speed to separated sub-frames. CONSTITUTION:A serial/parallel conversion circuit 11 and a reception circuit 13 are provided to the input side of a communication control equipment 1, a parallel/serial conversion circuit 12 and a transmission circuit 14 are provided to the output side respectively at each sub-frame and bit string and the location of a bus-frame sending a packet is made variable between the said reception circuit 13 and the transmission circuit 14. The high speed frame sent from a high speed transmission line is demultiplexed into the sub-frame assembled with the data of the same bit only by the serial/parallel conversion circuit 11, received by the reception circuit 13, processed by a terminal section 15 and sent while being converted into a high speed frame by the parallel/serial conversion circuit 12 via the transmission circuit 14 in the unit of sub frames in case of the transmission. Thus, the reception circuit 14, the transmission circuit 14 and the terminal section 14 have only to be operated at the speed of the separated sub-frame.
申请公布号 JPS62147838(A) 申请公布日期 1987.07.01
申请号 JP19850287779 申请日期 1985.12.23
申请人 FUJITSU LTD 发明人 MATSUDA MASAHIRO;FUKUDA HARUKI;TAZAKI TAKASHI;AWAZU TOMOHIKO
分类号 H04J3/08;H04L12/42 主分类号 H04J3/08
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