| 摘要 |
PURPOSE:To eliminate the need to match the timing of a timing signal with that of a clock signal strictly by providing a means which obtains a pattern signal corresponding to the AND result between a signal synchronized with an original pattern signal and the timing signal with the output of a switching means. CONSTITUTION:When the minimum interval between timing signals TG that a timing signal generating circuit 11 can generate is Dmin, a time (d) is determined on condition d<=Dmin and the circuit 1 outputs a switching signal LTd which is 1 when set timing tg is <=(d) from the beginning of its cycle. In an N cycle, the signal TG is nearby the timing of a clock TO. At this time, the signal LTd is 1 because tg<d, and a multiplexer (switching means) 13 selects the signal TV having almost the same timing with the clock TO. An FF 1 is set with the signal TC of this timing and pattern signals PAT and the inverse of PAT are ANDed correctly with the signal TG.
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