| 摘要 |
A serial DAC comprises two shift registers having their data input terminals connected together for receiving serial binary data. The shift registers are clocked alternately, whereby each shift register is clocked at substantially half the rate at which data is applied to the data input terminals of the shift registers. Two current switches are associated with the shift registers respectively, each switch being operative to steer input current to one of two output terminals if the data output of the associated shift register is a digital 1 and to steer input current to the other output terminal if the data output is a digital 0. Two current sources supply equal, constant currents to input terminals of the two current switches respectively. A third current switch has two output terminals connected to the input terminals of the first and second switches respectively, and is operative to steer its input current to its two output terminals in alternating fashion, switching between its two output terminals at the same rate as the shift registers are clocked. A third constant current source supplies the third switch with an input current equal to that supplied by the first and second sources, and the current supplied by the third current source is added alternately to the current supplied by the first source and the current supplied by the second source.
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